Functional verification systems, including hardware emulation systems and simulation acceleration systems, utilize interconnected programmable logic chips or interconnected processor chips. Examples of systems using programmable logic devices are disclosed in, for example, U.S. Pat. No. 6,009,256 entitled “Simulation/Emulation System and Method,” U.S. Pat. No. 5,109,353 entitled “Apparatus for emulation of electronic hardware system,” U.S. Pat. No. 5,036,473 entitled “Method of using electronically reconfigurable logic circuits,” U.S. Pat. No. 5,475,830 entitled “Structure and method for providing a reconfigurable emulation circuit without hold time violations,” and U.S. Pat. No. 5,960,191 entitled “Emulation system with time-multiplexed interconnect.” U.S. Pat. Nos. 6,009,256, 5,109,353, 5,036,473, 5,475,830, and 5,960,191 are incorporated herein by reference. Examples of hardware logic emulation systems using processor chips are disclosed in, for example, U.S. Pat. No. 6,618,698 “Clustered processors in an emulation engine,” U.S. Pat. No. 5,551,013 entitled “Multiprocessor for hardware emulation,” U.S. Pat. No. 6,035,117 entitled “Tightly coupled emulation processors,” U.S. Pat. No. 6,051,030 entitled “Emulation module having planar array organization,” and U.S. Pat. No. 7,739,093 entitled “Method of visualization in processor based emulation system.” U.S. Pat. Nos. 6,618,698, 5,551,013, 6,035,117, 6,051,030, and 7,739,093 are incorporated herein by reference.
Functional verification systems help to shorten the time it takes to design a customized application specific integrated circuits (ASICs) by allowing designers to emulate the functionality of the ASIC before a production run has begun. Functional verification systems help to ensure ASICs are designed correctly the first time, before a final product is produced.
According to some mechanisms, one of the outputs of an emulation processors data memory may be used to route bits from the memory to another emulation processor using a read port of the memory device. The desired destination may be, for example, an emulation processor located in a different emulation processor cluster. The output would then be routed to a particular emulation processor, which would occupy a read port of the memory during the transfer, making such memory read port unavailable to a lookup table (LUT) of the emulation processor that would typically receive data bits from the memory read port of the memory to perform processing. Other accesses to the memory read port other than for routing purposes may also render the memory read port unavailable to the LUT. Thus, as many as one bit from each emulation processor in the emulator, or one-fourth of all processor evaluations for a four-input lookup table based processor, for example, could be occupied during an emulation step of the emulation processor. Thus the memory read port would not be able to be used as another input to a lookup table, thus eliminating some flexibility in the system. For example, a four-input LUT would temporarily only be usable as a three-input LUT. It may be desirable to be able to send a value from a data memory to an alternate location outside of the processor where the data memory is located while still being able to use the full functionality of the LUT. Thus, for at least these reasons there is a need for an improved method and apparatus for selecting a memory read port.